Very Long Instruction Word (VLIW) Core
Execution units on two clusters for VLIW parallel processing at the instruction level
four 32-bit integer ALUs, two 64-bit shuffle/ partitioned add units, and two 128-bit multimedia units
128 32-bit general purpose registers, which can be treated as sixty-four 64-bit general purpose registers
thirty-two 1-bit predicate registers
eight special 128-bit registers
Native SIMD (single instruction multiple data) operations for parallel processing at data level
Memory Hierarchy
32KB four-way set associative non-blocking write-back data cache and 32KB two-way set associative instruction cache
Separate MMU (memory management units) data, instruction, and DMA
Glueless high-speed SDRAM/SGRAM interface, supporting up to 128 MB
Coprocessors
Variable Length Encoder/Decoder (VLx): a RISC coprocessor, fully programmable in C, that offloads bit-serial tasks from the VLIW core
Video Filter: a coprocessor for scaling of video with 4 (vertical) x 5 (horizontal), 3 x 5, or 2 x 5 tap filters
Fully programmable 64-channel DataStreamer DMA controller
DES engine for content protection
Integrated Peripheral Interfaces
PCI Bus: 3.3V, 33 MHz/66 MHz, 32-bit, PCI revision 2.2 compatible, internal host arbitrator
Inter-IC (IIC) serial I/O bus control port
Programmable format 64-bit/32-bit SDRAM controller, requiring no additional glue logic
Flash ROM read/write interface controller
Control signals for external video VCXO timing control loop for MPEG transport clock recovery
S/PDIF (IEC958) and IIS serial audio I/O ports
Two multipurpose ports, each of which can function as either an ITU-R BT.656 video decoder input port or a TCI (Transport Channel Interface) port
8-bit ITU-T BT.656 video encoder output port
1-bit serial or 8-bit parallel MPEG TCI (Transport Channel Interface) port to network interface modules
Programmable SVGA DRC (Display Refresh Controller) with 24-bit (8-bit x 3) 135 MHz digital-to-analog conversion
Digital RGB for supporting 12-, 18-, and 24-bit video streams, driving digital display panels
IEEE-1149.1 JTAG boundary scan compatible
Benefits
The BSP-15 chip matches or exceeds cost/performance features of fixed-function chips while adding exceptional flexibility to respond to rapidly evolving standards with software implementation changes.
The BSP-15 chip's C programmability simplifies and shortens the application development cycle, there by reducing time to market and enabling heightened responsiveness to changing market demands.
The BSP-15 chip's power and versatility allows it to function as the main processor in a single-processor embedded system, making it possible to build simpler, lower-cost systems.
Applications
The applications for the BSP-15 chip include digital cameras, hand-helds, imaging, media gateways, set-top boxes, telematics, video conferencing, video security, video head-end, and etc.
Development Support
The BSP-15 has a complete set of development tools, which include iMMediaTools software development kit, reference boards, and 3rd party software.
BSP-15 Chip Specifications
Technology 0.15 m, TSMC
Performance 40 GOPS @ 400 MHz
80 8-bit SIMD operations/cycle
16 16-bit MAC operations/cycle
BSP-15 parts
(CPU frequency,
SDRAM frequency)
BSP-15-300
BSP-15-350
BSP-15-400
283 MHz, 141 MHz
351 MHz, 117 MHz
405 MHz, 135 MHz
I/O voltage 3.3V
Packaging 352 BGA
These are just chip specs not what it can record or playback.