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post #361 of 744 Old 03-20-2003, 11:41 AM
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Follow up to my previous post :

Here's a closeup that shows the holes in the PC board where the wires attach. Much easier than trying to solder to the chip pins.

Each wire in the picture (from top to bottom) corresponds to the following input signals on the SDI board:
  • D2
  • D3
  • D5
  • D4
  • D6
  • D7
  • D8
  • D9
  • CLK (red)
--Dan
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post #362 of 744 Old 03-20-2003, 11:54 AM
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Ok... from reading the application note... it seems like in our streams the EAV/SAV 'space' is empty... so it looks something like this....
Code:
(EAV) 00 00 00 00 < BLANKING > (SAV) 00 00 00 00 <Start of video line>
      |__4cc____| |___268cc__|       |___4cc___| |_____1440cc________|
Am I wrong?

We need to do this:
Code:
(EAV) FF 00 00 XX < BLANKING > (SAV) FF 00 00 XX <Start of video line>
      |__4cc____| |___268cc__|       |___4cc___| |_____1440cc________|
Thus, the spacing is there, just need to insert the codes.

As for the XX (or XY in the application note), all that is used for is to tell it if it's a EAV (FF), or SAV (00)... In figure 6, I see the table for the line numbers etc. I think that is used.

dhnjp1:
Thanks for the closeup shot for the RP82
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post #363 of 744 Old 03-21-2003, 02:52 PM
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Quote:
Originally posted by mavromatis
Ok... from reading the application note... it seems like in our streams the EAV/SAV 'space' is empty... so it looks something like this....
Code:
(EAV) 00 00 00 00 < BLANKING > (SAV) 00 00 00 00 <Start of video line>
      |__4cc____| |___268cc__|       |___4cc___| |_____1440cc________|
Am I wrong?

We need to do this:
Code:
(EAV) FF 00 00 XX < BLANKING > (SAV) FF 00 00 XX <Start of video line>
      |__4cc____| |___268cc__|       |___4cc___| |_____1440cc________|
Thus, the spacing is there, just need to insert the codes.

As for the XX (or XY in the application note), all that is used for is to tell it if it's a EAV (FF), or SAV (00)... In figure 6, I see the table for the line numbers etc. I think that is used.

dhnjp1:
Thanks for the closeup shot for the RP82
You're on the right track. the space is always there. The pixel count remains the same, EAV/SAV or not. You just need to generate the XY codes. As I said, you may get away ignoring the protection bits hy setting them to 0 or F. But once you get into your FPGA design you will see how easy they are to generate. They are just boolean operations between H@V. Not much unlike RS232 parity generation.

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post #364 of 744 Old 03-21-2003, 04:24 PM
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Glimmie... thanks for the info... I'm familiarizing myself with the FPGA software and have already created a counter... yippy... I know it sounds trivial, but I had no clue how to do it in the FPGA software... so it took me an hour to figure out... I understand the interface now... so I'm going to work on the logic this weekend.

I do have a question about the XY codes... each EAV/SAV code needs to be 4 clock cycles... I take it the XY part of the code is only 1 cycle, either be FF or 00 depending on the H,V,CLK combination (run though logic Roberto posted). That's the only thing I'm not understanding. Please let me know if the XY code is only 1 cycle, 1 byte... either FF or 00.

Thanks,
Danny
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post #365 of 744 Old 03-21-2003, 10:39 PM
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yes the XY code is one cycle, but no isn't either FF of 00. It's a combination of several bits as stated in my previous post. Because the msb of the byte is always 1, you can never have 00. You have to build logic which generate the other 7 bits from H V and clk. The mentioned protection bits are generated from XOR combinations of H V and F;

P3 = V xor H
P2 = F xor H
P1 = F xor V
P0 = F xor V xor H

This means before you can generate these bits you have to generate the F
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post #366 of 744 Old 03-23-2003, 10:59 PM
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I've got some more show-and-tell...

Here is my board all soldered up:
http://www.mavromedia.com/tofrom/board_wires.jpg

Here is my board all installed:
http://www.mavromedia.com/tofrom/board_installed.jpg

Here are some signals from my scope:

This one is from the D0 line
http://www.mavromedia.com/tofrom/D0-wave.jpg

Just a x5 mag of the D0 line
http://www.mavromedia.com/tofrom/D0-closeup.jpg

I'm wondering if that break is where I need to put my EAV/SAV codes?? I also have made some progress on my FPGA logic... I should have something by next week... can't wait to see if I actually can get this thing to work...

Danny
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post #367 of 744 Old 03-24-2003, 09:30 AM
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Hi Danny,

Is the BT601 a 8-bit signal + HSYNC + VSYNC + 1 clk?

Dave
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post #368 of 744 Old 03-24-2003, 09:52 AM
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post #369 of 744 Old 03-25-2003, 01:53 AM
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To the generous AVS member:D :D :D

I received PC Board. Thanks again !

I also received NS CLC021VQZ-5.0 yesterday. I will order today some cms resistors and condensors.

My SDI mod adventure will finally be begun.:p :p :p

Could somebody give me the suitable ref. of Belden cable for sdi application, please ?

*** Yes, of course, it's Belden 8281 coax cable.! :D
--- Thanks :p
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post #370 of 744 Old 03-25-2003, 09:14 AM
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Quote:
Originally posted by ysbk

Could somebody give me the suitable ref. of Belden cable for sdi application, please ?

*** Yes, of course, it's Belden 8281 coax cable.! :D
--- Thanks :p
For a run of 25 feet or less, RG59 is fine. 8281 is also a good choice up to 300 feet. Most professional installations today use Belden 1694 or 1505A as they are foam dielectric and better suited SDI.

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post #371 of 744 Old 03-25-2003, 10:18 AM
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Hi Glimmie

Thank you for your answer.

For the BNC connectors, should I absolutely use 75 ohm version or could I use 50 ohm version, which is easier to find.

To mount on the PCB, it's the same problem, I visited today 3 electronic retailers, but nobody has 75 ohm BNC connector to solder on PCB. :mad:
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post #372 of 744 Old 03-26-2003, 11:15 AM
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Look for a "security camera" or CCTV cable. I'm using a $4 "security camera" cable, 6ft RG59 75ohm with BNC connectors, that works perfectly fine. For the price, it doesn't hurt to try it!

--Dan
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post #373 of 744 Old 03-26-2003, 04:56 PM
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Quote:
Originally posted by ysbk
Hi Glimmie

Thank you for your answer.

For the BNC connectors, should I absolutely use 75 ohm version or could I use 50 ohm version, which is easier to find.

To mount on the PCB, it's the same problem, I visited today 3 electronic retailers, but nobody has 75 ohm BNC connector to solder on PCB. :mad:
If you are just connecting your SDI DVD player to a scaler, then a 50ohm connector is OK. The slight impedance mismatch should not be a problem in this limited application.

It's when you have hundreds of cable feet coupled through 50ohm patch bays and throw in a few 50ohm BNC connectors along the way and you get problems.

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post #374 of 744 Old 03-27-2003, 05:13 AM
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Hi dhnjp1 and Glimmie,

OK, I made a cable with RG59 and 50ohm BNC connectors. I will see what happens.
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post #375 of 744 Old 03-28-2003, 04:31 AM
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I'm interested in building a CLC021VQZ-5.0 eval board. Is someone willing to sell me a blank PCB board. If not can someone recommend a generic PQFP 44 pin generic adapter which I could buy. thanks,
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post #376 of 744 Old 03-29-2003, 05:07 AM
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Hi,

I'm not sure if this is the right place to post this question, but this thread seems to have a large readership that is familar with BT601/BT656 and the differences between the two.

I tried an experiment using my Cybermail card and an old Apex AD-600 that I wasn't using anymore.

The Apex uses an ADV7170 chip, which supports 601 and 656. I wired the GPIO pins and clock of the ADV7170 directly to the corresponding pins on the BT878A. I used a ribbon cable (using alternate leads and connecting the unused leads to ground). I installed the Silk WDM drivers and the latest DScaler. I can select the SDI input (SDI 100 card selected as input in DScaler) and I get a picture. The problem is that the picture is split into quarters and those quarters are displayed in opposite corners of my monitor.

Is this what the picture would look like if the ADV7170 was using BT601 instead of BT656? Or is it noise from my 18 inch ribbon cable? Or do I just not have DScaler set up correctly?

Bob
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post #377 of 744 Old 03-29-2003, 05:23 AM
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Hello Bob,

A screenshot would help.

regards,

Roberto
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post #378 of 744 Old 03-29-2003, 07:37 AM
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Roberto,

Here is a low resolution capture from DScaler. It looks awful, but it shows the screen layout.



Bob
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post #379 of 744 Old 03-29-2003, 08:00 AM
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Bob,

I don't see the image !

regards,

Roberto
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post #380 of 744 Old 03-29-2003, 09:31 AM
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Roberto,

I'm not having much luck with images. The server partially bounced my first attempt to post the image here because I had already posted the image in the test area. I deleted that copy and tried to put it here again and the server rejected it because I was trying to post more than one post in 60 seconds...

Maybe the third try will be a charm...



Bob
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post #381 of 744 Old 03-29-2003, 09:53 AM
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I don't think it's a problem with your wiring. I think your out of luck and you dvd player is using bt601. The black space is Horizontal and vertical blanking. The bt878 chip is also capable of handling bt601, you have to include h and v sync from the dvd player. However dscaler programs the bt878 chip to accept bt656 stream on the gpio only.

update
I looked at the dscaler source. The definition : BT848_DVSIF_CCIR656 is set in the file bt848_defines.h to 0x01. I think if this is set to 0x04 the gpio port accepts bt601 with h and v sync.

regards,

Roberto
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post #382 of 744 Old 03-29-2003, 12:05 PM
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Roberto,

I may give it a try and hook up H and V. I'll think about it. I can't do anything until Monday, because I did the soldering at work so that I could use a microscope and fine tip soldering iron to attach to the BT878. I may just switch over to my RP56 since I've gotten my feet wet on the Apex without zapping it.

If I do hook up the H and V signals on my current setup, what compiler is DScaler built with?

Bob
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post #383 of 744 Old 03-29-2003, 01:10 PM
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Look on : http://www.dscaler.org/developers.htm

regards,

Roberto
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post #384 of 744 Old 03-31-2003, 05:12 PM
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Hey there... I was out of town for a week... I'm planning on working on the FPGA stuff again this week... has anyone else made any progress with this? I worked on the logic while on the plane... amazing how much stuff you can get done when you can't get distracted... :)

I've got the logic down to do things on each of the 4 clock cycles... now I need to add the 268 cycle counter, then the other 4 clock cycle counter, and finally the inserting of the XY codes.
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post #385 of 744 Old 03-31-2003, 11:45 PM
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Hi All !

First of all, I want to thank to everybody who participate in this excite thread, and especially to the generous member who gave me the chance to continue my adventure.

I did it with the help of my friend, who doesn't smoke

Here are some pictures of Panny A7 DA board and of sdi mod.

The general view of bottom side :
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post #386 of 744 Old 03-31-2003, 11:46 PM
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Closer look of bottom side near Mpec decoder :
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post #387 of 744 Old 03-31-2003, 11:48 PM
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The general view of upper side :
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post #388 of 744 Old 03-31-2003, 11:50 PM
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A closer look of upper side, near ADV 7172
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post #389 of 744 Old 04-02-2003, 11:48 AM
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So I'm learning Verilog right now... got my counter to work... this stuff is pretty easy once you get the hang of it. Finally, I can write code instead of graphically placing gates and counters.

I'm working with a few people on the forum... once I get something to work... I'll write and post a how to insert EAV/SAV codes with a FPGA.

Danny
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post #390 of 744 Old 04-02-2003, 03:40 PM
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Here is my Verilog code so far... I now just need to add the logic for the XY codes. This Verilog FPGA stuff is pretty cool... I've got about 20% of the pins left on the FPGA... I hope it all fits

Thanks,
Danny

 

sdicodeembedderntsc.txt 3.0263671875k . file
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