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Join Date: Apr 2003
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|Originally posted by montreal
Even though my question is treated in two other threads, I raised the question here because DWE referred above to a MID3 type parameter and I hoped he also knew about this mysterious MID1 DPSW parameter. Sorry to go off on a tangent.
Adu, you can only get a scrolling bar by having the incoming 1080i signal present.
My suspicion relates to what you have mentioned in your other thread about the difference between 2002 and 2003 where some circuits are bypassed for better PQ.
By chance, the solution to stopping the scrolling bar on 2002 models is also to completely bypass the circuit which up-converts 720p, and 1080i to 1080.0001i, for lack of a better name. Without the patch activated bypass circuit, I wondered if 480i and 480p were also being up-converted as well, maybe both to 1080.0001i?
The scrolling bar is due to the difference between 1080i and 1080.0001i, roughly one hertz. When bypassing the up-conversion circuit which is only reasonable for 480p and 1080i (480i and 720p both need up-conversion), you also eliminate using the two redundant a/d and d/a conversions for a better PQ.
To know that the bypass is working, one has to have over 2 volts present across pin 5/6 of connector CN3203 of the B board (TH CONTROL). This is the signal that turns on the bypass circuit. If it fails to ever turn on with the HDPT patch (I assume it always does when required), then I was wondering if the MID1 DPSW patch increased the chance that it would turn on.
This second patch (DPSW) was specified for the XBR2 but not the HS500/XBR800 and I assume that the HA3 chassis may have more privileges than the DA4 chassis since their owners paid more money for the former.
Also the TH CONTROL signal comes directly from the delicate main CPU chip outputting a MOS level signal.
In a month or two I plan on measuring the presence of my TH CONTROL signal when playing a 480p or 1080i source. I may even attach a buffered LED pilot light to come on when the signal is present.
|Originally posted by montreal
HDPT is under category OP.
As for whether 480i and 480p are up-converted to 1080i? We know that without the HDPT patch, every input signal must go through the conversion circuit.
1080i is up-converted to 1080.0001i causing the scrolling bar, and 720p is up-converted to 1080.0001i and 480i and 480p are up-converted to something.
The reason I add .0001 to the format is that we can't be sure that the horizontal frequency coming out of the converter is a precise copy or multiple of the source frequency. It is internally generated from an independent source.
So the question is if 480p goes into the up-converter, does it come out of it as 480.0001p or 960.0001i or 1080.0001i? All would look about the same because the converter does a good job. And would 480i come out of the converter as 960.0001i or 1080.0001i?
Switching on the bypass circuit for 480p and 1080i input signals allows the horizontal scanning rate to lock onto the incoming signal and completely eliminate any slow or fast scrolling vertical bar.
My guess is that all formats (480i,480p,720p, and 1080i) come out of the converter at 1080.0001i. The 1080.0001 timing is subdivided from a fixed crystal oscillator and it would be the one and only native scanning rate for the TV. You would need a oscilloscope to see it or hold a transistor AM radio near the back of the TV and tune it between stations and listen if the whining sound changes pitch when changing inputs from 1080i to 480i to 480p.
In other parts of the world, multiple formats may all get up-converted to one fixed internal clock generated scan rate as well. Perhaps in other countries the scan rates of the input signals are never very close to the TV's native scan rate so that the vertical bar scrolls too fast to be noticed.
In North America, Sony made the mistake of choosing a native scan rate too close to the up-converted scan rate ( a 1 hertz difference).
|Don't tell me I am the only one with Ctrl-Alt-Del on my remote control!|
|So I guess, here's my question,.... just to kind of break this down. Do you think that switching HDPT to 0 could reroute 1080i so it bypasses some of the processing or conversion that's being applied to the other signals?|
|5) When HDPT=0, none of the MID..... sizing and positioning adjustments I've been using have any effect on the "new" 1080i picture. Like everything else though, it is resizeable with the global sizing and positioning controls in 2170D-1 (VPOS, VSIZ) & 2170D-2 (HPOS, HSIZ).|
|Changing HDPT to 0 bypasses completely the DRC chip (re-scaler) and the MID chip (twin view) completely. This explains why you see no effect from changing the MID parameters. What you see on the screen is the raw 1080i signal, be it from the components input or the DVI input.|
|If the bypass control signal is also being activated for 480p, then this could explain why you are getting a better PQ on 480p now that HDPT has been changed to 0.|
|Remember that when the bypass circuit is activated, a lot of video processing is really bypassed.|
|The 910's display format is 1080i. If you feed it with 480i, 480p, or 720p native signal, the 910 would just use the internal conversion circuitry to convert the signal to 1080i. Your 480i/480p/720p PQ is limited by the quality of the 910's format converter. In the end, it's still 1080i. And yes, I have seen slight evidence of "stairstepping" artifacts in a few HD scenes. It's very very minor. I don't think, even with progressive scan, you can completely eliminate it unless you increase the resolution to an obscene level, in the tens of thousand range.|
|Perhaps the greater horizontal resolution is what's kicking it into 540p up-conversion. (?)|
|My suspiscion is that it may be disabling the circuit which converts all signals to your "1080.0001i".|
|I agree that HDPT must be changed only when the selected input is RF (Video 1?).|
|When you changed DPSW, were you doing this with the input set to Video 1 (RF)?|
|Changing the DPSW is only required for the HA3 chassis (XBR2) and is only done along with HDPT while video5 (components) is selected. For the DA4 chassis (XBR800/HS500), only HDPT is changed and only while video1(RF) is selected.|
|Did you loose the on-screen display at the same time as you changed DPSW?|
|The on-screen display text is injected into the video path at the CRT drive circuit, after the DRC and MID.|
|I'm still curious as to why DPSW is changed on the KD34XBR2 but not on the XBR800.|
|I was one of the unbelievers regarding the different circuitry on the 2002 and 2003s.|