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post #721 of 732 Old 03-30-2011, 12:12 AM
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Originally Posted by HFGuy View Post

Armin in that figure you have posted the PLL will have a very LOW loop bandwidth when locked.

The what???

That design is a dual-PLL clock recovery system. First stage PLL exists in the CD8412 which does a good job of locking to the input, but provides no jitter attenuation below 10 KHz (wonder how many millions of devices used that as their sole clock generator in its time). The author designed the secondary PLL with Fc of 1.5 Hz to substantially improve the performance of the whole system with respect to jitter. It is an example of what Andre and I have been talking about in previous posts.

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With a DPLL it is simple to have a loop BW below 1Hz. Basically (very basic but close enough for internet forums) below the loop BW the output of the PLL will have the phase noise characteristics of the input, in this case the clock from the SPDIF signal. Above the loop BW the PLL will have the phase noise characteristics of the VCO. With the loop BW set to 1Hz all of the jitter of SPDIF is eliminated, and the phase noise of the VCO can be VERY low (-140 to -160dBc/Hz @ 1Mhz offset)

And how long will it take you to lock to the incoming signal if it is off by say, 1KHz from the VCO? How do you even know it will lock? How will it lock to multiple sample rates? And do you really mean a low-q VCO or VCXO?

Please don't mind my cranky response here . I have come awfully close to firing two senior electrical engineers who designed PLLs which did not perform in real-life, costing significant damage to our business until we brought in expert PLL designers who knew more than cut and past form app notes and college textbooks. There are lots of conflicting requirements to be met, combined with good analog and digital design experience -- stuff that takes a lot of real experience to gather.

If you are convinced you can design jitter free PLLs, then I am sure a number of DAC companies would love to hire you. Perhaps Carl can refer you to Dataset folks.

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post #722 of 732 Old 03-30-2011, 12:39 AM
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Adaptive loop bandwidth or other acquisition aids.

P.S. I am far from a cookbooking engineering. My Phd thesis is on an UWB frequency synthesizer. The required lock time was 9.5 ns and covers from 3.1 to 10.6 GHz.
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post #723 of 732 Old 03-30-2011, 08:22 AM
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Originally Posted by amirm View Post

And how long will it take you to lock to the incoming signal if it is off by say, 1KHz from the VCO? How do you even know it will lock? How will it lock to multiple sample rates? And do you really mean a low-q VCO or VCXO?

Is this 1kHz (2.2%) real life example? Did they use RC to generate that magnificent clock?
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post #724 of 732 Old 03-30-2011, 09:28 AM
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Is this 1kHz (2.2%) real life example?

It can be. Specification allows up to 5% variation from nominal rate. For even the lowest sampling frequency of 44.1 KHz, this is 2.2 Khz.

The spec further acknowledges the main application for this which is to synchronize audio clock rate to video. I have seen video capture cards which do this. And seen it happen when audio is multiplexed with video for publishing on the web or optical disc. One or the other element needs to be master which is almost always is the video.

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Did they use RC to generate that magnificent clock?

No, per above it is not an accuracy issue. It is a matter of synchronization and since the spec allows it, why not simplify your life and go there? The alternative would call for sample rate conversion on the fly to meet the exact rate which is not pretty from cost point of view and performance.

I also would not be surprised at all if motherboard S/PDIF output used shortcuts for its clock synthesizer and not run at precise rates. At least in the old days of motherboard design, it was common to use some other clock you had and apply a divider to it to get close enough and call it done. So even though the source is crystal controlled, the rate is nevertheless not the nice numbers we are used to.

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post #725 of 732 Old 03-30-2011, 10:22 AM
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While I have used logic and reasoning in my posts to explain my side of the argument you feel it necessarily to minimize and belittle me. Thanks for being such a gentlemen, I no longer feel the need to participate here.

P.S. My grandparents have been using a TV since it was almost first invented, doesn't mean they understand how it works better than I do.
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post #726 of 732 Old 03-30-2011, 10:47 AM
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HFGuy,

Don't drop out. It has been an interesting discussion and many of us are learning from your exchanges. Amir is a good guy, its just that sometimes he gets a little curt (I'm guessing its when the engineers piss in his coffee ).

Ignorance more frequently begets confidence, than it does knowledge. Charles Darwin
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post #727 of 732 Old 03-30-2011, 01:51 PM
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Quote:
Originally Posted by Raul GS View Post

HFGuy,

Don't drop out. It has been an interesting discussion and many of us are learning from your exchanges. Amir is a good guy, its just that sometimes he gets a little curt (I'm guessing its when the engineers piss in his coffee ).

+1. Also I thought we all agreed not to tell him about the coffee thing.

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The reason for that is many of these extreme "high end" products are built in a garage or perhaps a 700sqft industrial space. There is not enough margin to even enlist the services if a surface mount assembly shop. I'll even speculate many of them can't even afford the CAD software that supports modern devices like BGA.

I'm not sure this is a good excuse anymore. OK, maybe good CAD software is sorta expensive ($20Kish?), but fabrication of really complicated circuit boards is fast, and not that expensive. We just made a 10-layer HDI (ie. laser-drilled vias that go down only 1 layer) board, of which 30 prototypes were fabricated, assembled, and delivered in about a month for around $20K. Each board has a $200+ FPGA in that cost, too. A simpler 4-layer board for typical audio applications could be done even faster and cheaper, and there are lots of small contract manufacturers around who specialize in small prototype runs.

I think the big part of the problem is lack of knowledge, and therefore lack of appreciation of how a small investment in good tools and design can yield a big return.

Two great examples come to mind: Benchmark and Centrance. We all know about Benchmark already, but the Centrance people are pretty damned impressive, too. For example, they've proven how adaptive USB can be essentially jitter-free in their $400 DACport product, and the insides of their DACmini show that they know how to use current good design methodologies.

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Originally Posted by amirm View Post

Question here is what can impact the timing/zero crossing point.

I think where we are talking past each other is that you are assuming people just clock straight off the input signal, while I believe you need some form of clock recovery sophistication. The former has to worry about jittery zero-crossings, while the latter doesn't. It's not expensive to do it too, as Centrance and Benchmark have shown. It's simply a matter of design competence.

--Andre
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post #728 of 732 Old 03-30-2011, 01:54 PM
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Quote:
Originally Posted by amirm View Post

It can be. Specification allows up to 5% variation from nominal rate. For even the lowest sampling frequency of 44.1 KHz, this is 2.2 Khz.

The spec further acknowledges the main application for this which is to synchronize audio clock rate to video.

This is the obvious reason why USB>SPDIF crutch wouldn't work well in such application: the entire thing should be slaved to video or it wouldn't work. Even separate audio-only master clock will not help: you'll need to resample audio in such case or it will run out of sync.

I also can't understand the logic why adding properly designed PLL is overly complex decision, but adding $900 USB->SPDIF converter is just fine.
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post #729 of 732 Old 03-30-2011, 01:55 PM
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Originally Posted by raul gs View Post

hfguy,

don't drop out. It has been an interesting discussion and many of us are learning from your exchanges. Amir is a good guy, its just that sometimes he gets a little curt (i'm guessing its when the engineers piss in his coffee :d).

+1
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post #730 of 732 Old 03-30-2011, 02:20 PM
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Originally Posted by Victor View Post
This is the obvious reason why USB>SPDIF crutch wouldn't work well in such application: the entire thing should be slaved to video or it wouldn't work.
We use the USB solution for music only. For video, you have secondary issues of compatibility given the non-secure aspect of the USB path. So HDMI is the solution there, good or bad.

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Even separate audio-only master clock will not help: you'll need to resample audio in such case or it will run out of sync.
I am not following this one. You mean in the context of USB audio on a PC? If so, the PC becomes a data pump and not running synchronously. So no resampling is needed.

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I also can't understand the logic why adding properly designed PLL is overly complex decision, but adding $900 USB->SPDIF converter is just fine.
I share the quandary with you . Here is the situation. I have added these converters to some of the best processors: Mark Levinson Dac/Processors and Berkeley Alpha DAC. I have added them to cheap boxes like Peachtree Nova. I cannot explain why it makes a difference up and down the tiers and why so much. I still remember the first time I tried it on the ML DAC. I had to switch back and forth to believe the difference.

The audiophileo also has a jitter simulator and triggering that even on the high-end processors changes the sound. Why would it if all the jitter is squashed out?

If you talk to Michael Ritter at Berkeley, he will over and over emphasize how you need the absolute best digital source to make their DAC sound good. I remember challenging him on that. After all, you think if you got a high-end DAC, you wouldn't need to jump through hoops like this. But according to him, you did if you wanted to get world-class sound.

Maybe some of this is due to secondary effects. That your PLL circuit itself is causing jitter elsewhere as it tries to do its thing. After all, the PLL is trying to eliminate the jitter from the source. It is not doing anything for the intrinsic clock jitter on the DAC. And when source jitter occurs, maybe the actions of its phase detector causes degradation elsewhere.

Maybe some of this is due electrical isolation offered by these converters. Clearly jitter is not the only reason audio fidelity is impacted. Perhaps cross coupling the systems without isolate degrades PLL or DAC performance.

We have the new Berkeley USB to S/PDIF converter on order so I should be able to test this effect more broadly.

This may be one of those situations where we confirm the observation and then work backward to find an explanation.

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post #731 of 732 Old 03-30-2011, 02:28 PM
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Originally Posted by amirm View Post
I am not following this one. You mean in the context of USB audio on a PC?
If so, the PC becomes a data pump and not running synchronously. So no resampling is needed.
This was in the context of HDMI A/V signal and interface shortcomings: you can do very little except accept the audio data as-is.
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post #732 of 732 Old 03-30-2011, 03:20 PM
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Originally Posted by AndreYew View Post
......A simpler 4-layer board for typical audio applications could be done even faster and cheaper, and there are lots of small contract manufacturers around who specialize in small prototype runs.
Yes, I do small internal projects where I work, we are not a product manufacture. I have been using Eprotos.com for over ten years now. Great service and quality. And they can go to 17 layers I think.

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I think the big part of the problem is lack of knowledge, and therefore lack of appreciation of how a small investment in good tools and design can yield a big return.

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