Originally Posted by 1031
How about this kind of config. This cuts clamp away but leaves brightness control and spotkill should work also? trimmer allows adjust pedestal to right level. I was little worried just to pull out that R36 and feed "pedestal voltage" to that line (spotkill doesent work then)
Yes, that circuit would do fine to correct/adjust pedestal, but adjusting the pedestal there I'm thinking is not why they're using that S/H circuit.
A clamp section here makes no sense in this section, so there must be something else going on here...
Look at my two test patterns. In them I'm showing two signals overlapping each other. I'm show them with both boards having the circuit enabled, and I'm also showing one with the circuit disabled.
The one showing the circuit disabled also shows a crippled low end linearity. Crippled meaning the low section of the tes pattern is not linear. To be linear, each step (bar) has to have equal space from the other. If you look at the bottom of the patterns, the spacing decreases on the last two bars.
That is the same linearity problem I've been talking about for the longest. based on the two comparison patterns, the S/H circuit seems to only correct the lower end of that pattern. The pedestal is irrelevant here, because it can be adjusted with the brightness control. And though the circuit also effects the pedestal, it's not effecting it to point an entire circuit should be needed to correct it.
Non linearity seems to be one of the drawbacks with direct coupling circuits. I was of the thought that R90 and R91 was the tweak to smooth things out on the boards, but it looks like they're also using that S/H circuit as well.
I can also understand why tse is not using the circuit. The problem has a lot to do with the components being used. By simply swapping in another IC for U2, you also risk throwing off the low end linearity. he must be doing something to control this well, because the older chips were terrible with linearity in direct coupled stages. The newer ones maintains the linearity way better, but still may need a bit of help.
Keep in mind. The linearity issues I'm talking about is fine for VESA and computer graphics applications. It's only a problem with HD signals and bringing out the best in low end detail and performance.
I'll get back to this later, but for now. I see need to keep the circuit in my boards.
Oh, you can also control the offset by using variance at pin 3 of IC 4 (10K pot to +/- 14 rails of U4 - w/100K to pin 3.
I plan to look into making a linearity pot to smooth out that lower end. for HD signals the goal should be to have each step exactly the same spacing from each other.