Reading through the Panasonic patent 20090021452A1 describing method of driving plasma display panel, I noticed one interesting thing that I did not see discussed elsewhere. Hopefully it's alright to post it here (or feel free to move it to Panasonic black levels thread or elsewhere you find it appropriate).
According to patent, there are three driving modes for the panel corresponding to panel/ambient temperature. The sensor (81) measuring the temperature is located as in FIG4A, 4B.
To precisely monitor the panel temperature, many sensors (81) would be required, which increases costs and complexity. Instead, Panasonic uses estimates values and correction values for high and low temperatures and the sensor is placed on circuit board (89) separated from panel (10) by heat conduction sheet (86), aluminum chassis (87) boss material (88) and air bubbles. This prevents local temperature changes caused by varying screen content. In the patent, there are also graphs showing correlation between actual panel temperature and sensor temperature from which the correction values are computed, but for simplicity I'm gonna leave them out.
FIG9 shows the logic for selecting the driving method (low-temp, normal-temp, and high-temp) according to sensor temperature (again, the actual selection is much more complicated according to patent using hysteresis characteristics and thresholds but I'm not gonna post them here since it's not necessary to get the big picture).
In next figures are the actual driving modes for APL >6%. FIG4A shows low temperature, FIG4B normal temperature, and FIG4C high temperature driving mode.
With low panel temperature, the discharge start voltage increases and the initializing discharge in the all-cell initializing operation is prone to become unstable (and pixel misfiring can occur). Therefore, the Vr (initializing voltage) is set higher for low temperature (VrH) and is lowered for normal and high temperature mode (VrC). However, with increased VrH voltage, MLL also rises. Therefore, the MLL in the first 10-20 minutes of operation (until the panel warms up and circuit switches to normal temp driving mode) is higher.
In normal temperature driving mode for APL >6%, there are two all-cell initializing operations (in first and fourth SF). When the panel switches to high temperature driving mode, another all-cell initializing operation is required (in sixth SF) to guarantee stable panel operation. Additional all-cell initializing operation has the effect of raised MLL (again). The similar algorithm is used for APL <6%, only the all-cell initializing operations are increased to two (from one) instead of three.
To sum it all up, in the first 10-20 minutes of Panasonic plasma operation, the MLL is increased because of higher VrH voltage and is lowered once the panel warms up and circuits switch to normal temperature driving mode. Again, if the panel temperature becomes too hight or the plasma is installed in high-temperature environment, the MLL rises because of additional all-cell initializing operation (from the patent it's hard to tell, what is the actual temperature that causes the panel to switch to high temperature driving mode, but my speculation is somewhere above 50-55°C for panel itself or 35=40°C for the temperature sensor (81)).
Anyway, since this is only a patent, it's not guaranteed that any of this is actually implemented in Panasonic plasmas, but from my observations I would say that at least some of it must be implemented as the MLL really is higher in the first minutes I turn on my P42G10E.
