Originally Posted by xrox FLOATING BLACKS EXPLAINED
Post created as a place to compile information describing the cause and reason for floating blacks. So far 4 patents describing the issue (aka – feature) are posted. The post is linked in the Zero Black Thread
- Black level changes depending on APL of screen (APL=Average Picture Level))Cause
- The number of all-cell initialization pulses are changed depending on APLReason
- At high APL the panel impedence causes a voltage drop (due to higher current) and pixels may start to misfire so an additional all-cell initializatin is peformed to compensate (re-priming the cells)Why Only Panasonic
- Other manufacturers just raise address voltage or width to compensate which impacts panel efficiencyDetailed Version
The phenomenon we see is an abrupt change in black level depending on the content on the screen. This is especially noticeable in black bar areas and while watching in low ambient light.
Below is some definitions to know before reading the patent literature.
Description of Panasonic REAL BLACK DRIVE (Panasonic)
- APL is the Average Picture Level (think of it as the % of the screen at full white)
- Initialization is the process where the pixel cell is prepared for stable operation (discharged in order to produce priming electrons (think “pre-discharge”) and discharged in order to create wall charge)
- All-Cell Initialization is when every pixel is initialized regardless if they are to be used or not (main contribution to black level)
- Selective Cell Initialization is when only cells to be used to emit light are initialized (no contribution to black level)
- Discharge start voltage is the voltage threshold at which discharge occurs above this voltage and no discharge occurs below this voltage.
Panasonic Patent application #20090021452
- 1 or 2 "all cell" initialization periods (every subpixel is initialized no matter what) depending on APL.
- All other subfields use "selective" initialization periods (only pixels that have previously generated a subfield)
- see end of post for more detail
(same patent that describes rising blacks)
Describes how the black level will shift at 6% APL (becomes darker below 6% APL and brighter above 6% APL). Notice the one large single pulse (initialization) for the <6% case and 2 large pulses for >6%APL case.
Patent also says that if a hysteresis characteristic is applied there will be two thresholds at 5% and 7% that will lessen the number of black level shifts. Black level become higher above 7% APL (2 all-cell initializations used) and then become darker below 5% (1 all-cell initialization used).
The patent does not clearly state the reason it is necessary. The patent does seem to suggest that the intended feature is a stable picture with higher contrast at lower APL (where it is important). The perceivable brightness shifting is an unwanted byproduct.Panasonic Patent application #20100253673
Describes the use of a combination of no initialization (ZERO BLACK
l) and REAL-BLACK-DRIVING (all-cell and selective cell initialiation). More specifically at least half the frames will be displayed by using no initialization (zero black) and the other half displayed by REAL-BLACK (1 initialization+selective initialization). To overcome stability issues with this method they change the address pulse width based on the ratio of zero black frames and REAL-BLACK frames used.
But if you read claim 3 you see that the ratio of these two methods is changed based on APL which again will create floating black levels.
The patent does seems to finally describe WHY
floating blacks is required on Panasonic designs.
In easier to understand terms the panel has resistance and thus when a lot of pixels are lit (aka – high APL) the voltage drops closer to the discharge start voltage
(see definitions start of post) . When this occurs the discharge delay goes up and the discharge probability goes down. The pixels may start to misfire. To compensate for this the panel uses an extra all-cell initialization because it provides extra priming particles that lower the discharge start voltage to a value that compensates for the voltage drop described above.Figure 11 from the patent
- see description belowFIG 11 description :
Think of the vertical axis as the time (address voltage pulse width) required to achieve stable addressing. And the horizontal axis as the time after all-cell initialization. Curves 1101, 1102, 1103,1104 all describe how the longer the panel goes without all-cell initialization the more time (or voltage pulse width) required to ignite it stably again. Now the different curves all have the same slope but represent different APL.
- 1101 – measured at 100% APL
- 1102 – measured at 50% APL
- 1103 – measured at 18% APL
- 1104 – measured at 1.5% APL
You can see that the higher the APL goes the more address voltage width is required to achieve stable operation (as per reason described above).Panasonic patents 7446734 and 7583240
Describe floating blacks in a 600Hz system using up to 5 black level shifts depending on APL.
Remember that the initialization step produces black level. More initialization the higher the black level. And APL can be thought of as % of the screen at full white. Check this out:Reasoning
(pay attention to bolded areas)Detailed description of Panasonic REAL-BLACK-DRIVE
(as best as I currently understand)All Cell Initialization:
-first creates excess wall charge state on all cells to [Q4]
-then downslope depletes wall charge in all cells to a normalized low level of [Q1]
- [Q1] is considered the "off" state (at this point all cells are at Q1)Address Period
- scans all subpixels line by line increasing wall charge in selected pixels to [Q3]
- [Q3] is still below the discharge start voltage
- [Q3] is considered the "on" state while all other pixels with low levels of wall charge are still in the "off" state of [Q1]Sustain Period
- applies AC voltage that discharges only the cells in the "on" state of [Q3]
- leaves the cell in the "on" state of [Q3] when completedSelective Initialization
- Only the cells in the "on" state (whith high levels of wall charge) are depleted back to [Q1] using the same downslope voltage ramp (see first plot) while all other cells are already at [Q1] and thus are unchanged during this step
- the panel wall charge is now normalized to [Q1] and again ready to be addressed