Poor man's SDI - Page 11  

My service manual for my DV-F07 will be here tomorrow... can't wait to see what encoder it has...

So I got my Service Manual for the DV-F07/727 and it looks like it will be an easy mod... all the pins are accessable from the daugherboard connectors! Check out the PDF... they are outlined in red. 5v, GND, D0-D7, and 27mhz Clock are all there. How can I tell if the SAV/EAV codes are in the stream? It seems like they are in the stream... no?

The PDF:
http://www.mavromedia.com/tofrom/DV-...07_Encoder.pdf

Let me know what you think...
Danny

Well i see Hsync and Vsync, this can't be good.

What's the easiest way to check if the stream contains the codes? I've got a scope... what pins do I probe?

Worst case.... is there a FPGA already out there that I can buy that will add the codes? Seems like something that should be available... the guys I asked seem to not want to give away/up their secrets... :(

i think you need a logic analyser to see the codes in the stream. Just probe the 8 databits.

I don't have access to a logic analyzer... I'm just going to wire it up and check to see if the image comes thru... now I just need to wait for the board to arrive... :(

Seeing Hsync and Vsync hooked up doesn't look good. You really should use an oscilloscope first. It may save you a lot of soldering. It's actually very easy to tell if the bus has SAV and EAV codes with a 'scope, as the codes use FF and 00, which means all 8 data bits go high then low simultaneously. Using a black screen as your 'test pattern', you can probe two signals at a time to verify the codes are there.

-Dylan

I don't think it's a secret or proprietary design issue. The circuit needs are well known to any broadcast video circuit designer. The issue is there is no one FPGA file that can account for all the different DVD/STB designs. Remember the internal H sync position in relation to the data stream is not defined. Nor is the vertical or frame pulse but that's far less critical. Take something as simple as polarity - some designs amy have postive H/V and some negative or a combination of the two. Your EAV/SAV embedder must take that into account.

As I mentioned Sony did make a chip that handled the entire 601 interface. But you have to design around this chip, it's not a drop in for existing designs. I you are in the SDI mod business, you have the tools to design FPGA's and there any minor changes are mouse clicks.

Sorry if this seems not too helpful but some DVD players are simple and others are best avoided if you don't have access to these tools.

I just thought of a poor man's EAV/SAV decector that could be easily built. Take a 74HC688. Gang all the A side pins together to a SPDT switch selecting Vcc or GND. Run your video data buss to teh B side of the comparator. Put a 74HC74 latch on the = output with an LED.

Reset the latch after power up and let it run. Test for both FF and 00 conditions. If they are both there you have EAV/SAV. You will know within 63us - the legnth of a scan line.

FF and 00 are illegal values in the video data and should not be there. These two codes are strictly reserved for EAV/SAV. In 10 bit system they are 3FF and 300 but our MPEG decoders are all 8 bits so we can ignore that.

No love on the SAV/EAV codes in the stream... so now... I need to learn more about how to create the logic to add the SAV/EAV codes... I'm in this to learn, I love challenges!! So any suggestions, help or guidance is greatly appreciated! I love this forum!

FYI, if you get deeper into this, EAV/SAV is more than just a FF and 00 code insertion. Those are the preambles. There are four additional bytes that specify fields and other things. There is also some primitive error correction codes that I don't think were ever exploited in receiving devices, EDH became the norm there as it's much more indepth. EDH fortunatly is not something us HT'rs need to deal with in our SDI systems.

Go to Yahoo and search eav sav just like that. This is a lot of good info. I tried it and was surpirsed at the number of good hits I got back.

I'm still at a standstill...

From what I have read... all one needs to do is add FF at the beginning of each scanline and 00 at the end... this will repeat about every 63us - the length of a scan line. I also take it one can use the current H-SYNC and/or V-SYNC line as a "trigger". There is no other values that are needed. Am I correct or way off?

Couldn't a PIC be used for this? Why does one need to use a FPGA?

Has anyone made any progress on this? The service manual says the polarity is Negative for the Pioneer DV-F07 H & V SYNC.

Sure seems like a PIC could be used. Not that I've ever looked at SDI streams. :) Cheap to prototype at least.

I think a PIC is not fast enough, you have to remember the bitrate is 27Mhz.

ah... wonder if there is something you can do to make it work...

with 27Mhz the samples are 37nS. You can fit more then 25 samples in a single uS.

I'm going to get this kit and try to figure out FPGA's...

http://www.hvwtech.com/pages/product...sp?ProductID=8

Mavromatis: Here is some light reading for ya.

SDI app notes from Xilinx.
http://www.xilinx.com/esp/prof_brdcs...ateral/sdi.pdf
http://www.xilinx.com/xapp/xapp288.pdf
http://www.xilinx.com/xapp/xapp298.pdf
http://www.xilinx.com/xapp/xapp299.pdf
http://www.xilinx.com/xapp/xapp625.pdf

Thanks for the links... I'll take some time to read them over... any pointers for 8bit stream vs. 10bit?

Does anyone have a FPGA schematic for inserting SAV/EAV codes? Basically, what I would like is a basic logic schematic that I can look at for reference... I take it I use the HSYNC as an input into the FPGA... right?

Here is an example of what I would like:
http://www.hvwtech.com/html_upload/images/maxscreen.jpg

Anyone want to help a person who wants to learn? :D

Thanks.

I started reading the datasheets for the Cypress parts that are referenced in the Xilinx appnotes and it appears that the CY7C9235 and CY7B9234 used together would work for implementations that don't include the SAV and EAV data on the bus.
Did i understand the datasheets correctly?
http://www.cypress.com/cfuploads/img...s/38-02012.pdf
http://www.cypress.com/cfuploads/img...s/CY7B9234.pdf
http://www.cypress.com/cfuploads/sup...smpte_eval.pdf

hmmm... it doesn't say anything specific about SAV and EAV codes... but it may... I don't know where you'd hook up the H-SYNC or V-SYNC to that chip... isn't that what the encoders without SAV/EAV codes use to lock the signal?

Which part is in the Sony (or other) DirecTiVo? I can take a look at it's datasheet and see if I can get all this stuff to mate up... The eval board white paper may also help (I'm looking at it now).

Anyone else interested in getting this to work on their DirectTivos please jump in.

I know the philips Tivo ones use this encoder:
http://www.semiconductors.philips.co...120H_21H_2.pdf

The more I dig into the datasheets, the more I'm convinced that this cypress part can dig out the SAV and EAV. I'm going to try building a prototype. Then, I'll just need something to test it with (not my TiVo on the first round).

Perhaps something in this app note will for the Cypress parts will help out.
http://www.cypress.com/cfuploads/sup...smpte_eval.pdf

Ah... I just read the data sheets more throughly... may be the answer... funny thing... no one has even posted about helping on the FPGA route... I get my FPGA kit soon... :D

The Cypress eval board is $700...

Well where is the frame start and end? How do you differentiate between field one and two? These items are encoded into EAV/SAV. That's why it's more than a simple FF/00 inserter. What I'm not 100% sure of is the error correction codes in the last byte (#4). I don't think they are needed. But if you are using an FPGA, they are quite easy to implement anyway.

after reading bits of the book "demystify video" i came to the conclusion it will not be easy to generate the eav/sav codes. It's a lot of programming.
First you can use the Hsync to trigger the eav insertion but not the sav insertion. Because the SAV code has to be inserted before the Hsync changes (therefor no trigger). You can accomplished this with a counter. However there is a difference between NTSC and PAL in the number of clock cycles between the eav and sav. If you want to compensate for this, you have to create also a NTSC/PAL detector.
Second you have to insert H V and F bits. I think H and V can be derived from the Hsync and Vsync but the F bit (field) has to be generated with a counter again.

I could be wrong, heh i'm not a video engineer but maybe Glimmie can give some more information :D

regards,

Roberto

Yeah, that Cypress eval board is a bit pricey. Using the eval app note, I've designed a much simpler circuit just using the 9235/9234 and a cable driver. It should be pretty simple. I think I have a line on the cypress parts so getting them shouldn't be too tough. I'll keep you guys in the loop.