Poor man's SDI - Page 12  

grayvader... I'll keep trying the FPGA route... definitely, let us know if the Cypress works. It may be the easiest route.

You need to generate and insert EAV/SAV, not "dig it out". It's not in the stream and that is the problem. True, some receiver chips do extract H&F from EAV/SAV but we aren't receiving, we are attempting to transmit SDI.

I reviewed the Cypress parts and frankly I'm not impressed. There are far better solutions from National and Gennum. These older chip "sets" invite PCB layout problems, especially with the limited PCB and breadboarding tools hobbiest folks can acquire. 270mhz is RF, plain and simple, and must be treated as such. The less that signal needs to be routed around on non-impedance controlled PBC traces, the better. The state of the art is a single chip solution which fortunatly are available and inexpensive.

These papers show how to implement SDI transmitters and receivers in an FPGA. This is targeted for highly cost sensitive and very compact designs both of which may not allow for an external SDI transceiver chip. It looks to me they also have included some analog functonality in some of their advanced FPGA blank parts.

But none of these designs deals with EAV/SAV. They assume it's already there.

For the purposes of this forum, I would stick with standard SDI transmitter chips and just use an FPGA to generate and insert EAV/SAV. That can be done with cheaper and slower parts, the bottom of the line Xilinx 4000 series.. Remember that while the data is in parallel form, we only have a 27mhz clock. That's not at all very fast in today's world of silicon.

Glimmie, that's exactly what i'd like to do... use the National SDI eval kit... but I need the FPGA before it to generate and insert the EAV/SAV. Where can I find out more about the logic needed to do this? Is the info I need in the Xilinx app notes? I need a starting point...

I'm planning on using a Altera 7000 series FPGA:
http://www.hvwtech.com/downloads/dat...000_Altera.pdf

Thanks!!!

Got my intro FPGA kit! For those of you that want more info on programming FPGAs... check the links below! Pretty cool examples on how to detect... it's weird that everyone is so secretive about the logic on adding the SAV/EAV codes? I have posted on this forum and to FPGA groups and no one will release any logic... If I figure it out... I'll tell how I did it. Now do I even use the HSYNC line in my logic? I'm thinking yes, based on the SDI PDF I looked at. Any one have a definite answer?

http://www.hvwtech.com/downloads/other/dueck_ch04.pdf
http://www.hvwtech.com/downloads/other/dueck_ch05.pdf

Hi all,

I've been following this thread with great interest since I was directed here by Matt (bonfiglio) from the HTPC forum. I asked the question about modding a DVD player and a Directivo. I have since ordered a couple of the SD021-5EVK kits from AVNET which are on back order. I am in the process of building a HTPC with a H3D card and would love to run SDI from my DVD and Directivo (which represents 90% of my veiwing) in the Halo card.

I only understand about 20% of what you guys are talking about but I am hoping that once mavromatis figures the Directivo Mod out (I'm sure he will eventually) he will share specific instructions with us not so gifted.

One question: Is there a list of DVD players/ Direct TV receivers that can be modified easily with out having to worry about the SAV/EAV codes?

Along with my Directivo, I have the following that I would like to add SDI to:

RCA DRD203RW DBS receiver.
Toshiba SD3750 DVD player
Sony DVP-s300 DVD player (if Toshiba can not be modded)

Has anyone had any luck with any of this equipment?

Sorry for sounding so naive but I am pretty new to all this but love to tear into things.


Tony

mavromatis:
I've never done any SDI mods, I'm just interested like the rest of the readers on this thread. I'm quick with google though. :)

I'm going to do some reading this week and get familiar with SDI and FPGAs... as soon as I make some progress I'll let you all know... my first mod will be the DV-F07 and DV-F727, both are Pioneer 300+1 DVD changers... these have the red chroma bug... but I don't mind that since the Rock Pro will allow me to correct it. The nice thing about the DV-FXXX Pioneer changers is that the MPEG encoder board (VQED) is removable and has nice solder pads that I can attach the wires to. I'll send up a picture of the board when I have a chance.

If anyone knows anything or has done the EAV/SAV insertion please post here... the only missing links are... do I need to use the HSYNC? And is there anything else I would need besides the D0-D7 pins from the encoder to the embedder? I know the clock, VCC and GND go to the SDI board. I should be getting my National and Koelewijn's board soon.

I've been debating whether it would be worth SDI'ing TiVo's... how much of a quality increase would one get? Anyways...once we get a nice EAV/SAV embedder, we can figure that stuff out... :)

mavromatis:
Perhaps modify a DVD player that has a EAV/SAV signal present, have the FPGA create your own EAV/SAV and then you can easily compare it to the 'working' one. Then you'll know you have it right.

Just finished the SDI mod for my Panasonic RP82, and it works great!!! Total parts cost was $45 (thanks to a fellow AVS member who generously gave me one of his blank PC boards). I'm even using a $4 BNC cable (6ft RG59 from a local electronics surplus shop).

The RP82 is very easy to modify! You don't have to solder wires onto the FLI2200 chip. The data and clock signals go through plated holes in the PC board (see the attached picture).

Here's my contribution to this thread:
I discovered the bt-656 output of the Panasonic mpeg decoder chip MN677531 is on pins 155-148, bits 7-0 respectively (there might be a pin between bits 3-4, so the lower 4 bits might be on pins 150-147...it was pretty crowded and hard to probe). These outputs go through 330 ohm series resistors, pass through the plated holes, and then connect to the FLI2200 pins mentioned earlier in this thread.

By the way, Digikey now has 95 CLC021 chips in stock (they were nice enough to get a tray of 96 when I back-ordered just 1 chip).

The attached picture shows the wires connected to the TOP of the video board, near the Panasonic mpeg decoder chip (which has the blue tape on it). The red wire is the clock signal. The SDI PC board sure is tiny, not much bigger than the mpeg chip!

--Dan

Dan,

Where did you find your blank PCB board ?

I wait for my EVK board since several weeks.:mad: :mad: :mad: :mad:

mavromatis, I'm in "sync" with you finally (i guess th pun was intended) so I'm also digging into how we program this FPGA. As I think about it, if we have to add the SAV/EAV into the data stream, all the signals will first have to go through the FPGA (along with the sync signals) where we'll have to add 0's and 1's based on those sync signals.
Since I'm new to the uncompressed digital video world I'm having to read up on how this stuff is coded and the relationship of SAV/EAV to hsync (and vsync?). Once that's figured out, it seems like the logic should be straight forward. If you want, we can continue this "offline." Just PM me and I'll send you my email.
-gray

OK... cool... I'll PM you offline... then post our findings back on the forum.

Here are some snapshots of the DV-F07 & DV-F727 Pioneer DVD Changers encoder "tap in" points.

VQEB Board
VQEB Closeup

Quick question about the RP82 and RP86... where can I find one for cheap... and are there any newer models with the same chips as the older ones? I'd like to use it as a reference...

And another question...
Do we have to build field and vsync flags into the data stream when we add the sav/eav codes back into the stream?

The Denon 1600, Panny RP91, RP82, XP50, and some XP30s all use the same MPEG decoder. Watch out for the RP62 though - if there is a "B" in the serial number then they slipstreamed in an MPEG decoder with an embedded DAC and it may not work for modification. The same goes for the new S35 and S55 - both use embedded DACs and deinterlacing in the MPEG decoder.

These are all straight bt656 so you needn't worry about the EAV/SAV missing.

Sorry I can't help much. I think my source has already given away his leftover boards. I gave up on getting a National eval board when the distributor I contacted 6 weeks ago couldn't get any reply from National on the lead time (after several phone calls and email).


Check the DVD Hardware forum to be sure, but I think the Panasonic XP30 and XP50 have the same mpeg decoder chip. The RP82 is discontinued, but is very popular. They sold for $200 when new and now used RP82 are selling for $350.

--Dan

So I talked to a guy at work that knows his stuff... here's what we came up with.

8 bits, 27mhz clock, hsync all come into the FPGA. In my case, the HSYNC is negative polarity which means that LOW is on... so when I get LOW from the HSYNC, I know that is the start of the new line... I set HI or FF for EAV... start a counter (need to figure out the length of Horizontal Blanking) and count down using the 27mhz clock... when I hit 0... I set the SAV to 00.... repeat...

That's it... so now I just need to figure out the length of the Horizontal Blanking... any one know off the top of their head? Glimmie?

a single line is build up as follow;

4 clock cycles EAV block
268 clock cycles Blanking NTSC / 280 clock cycles Blanking PAL
4 clock cycles SAV block
1440 clock cycles Active video

regards,

Roberto

You are refering to 27mhz clock cycles right? So based on those values... This is what I'm planning on doing...

Do I need to follow that exactly? I'd like to keep FF going thru the blanking then do 00 for 1 clock cycle... so...

When HSYNC goes HI... set Blanking to FF for EAV... keep it FF until 268 clock cycles... which I will then set to 00 for 1 clock cycle (SAV)... then do it again when I get HSYNC HI... will this work?

I can write the logic the way you said if need be...

I refer to the 27Mhz clock.
The EAV block and SAV block are build up as followed;
FF 00 00 xx (the xx is buildup using F H V bits)
the xx differs between EAV and SAV
I think your approach is a start, but it has to be more complex.

A nice document is http://www.intersil.com/data/an/AN9728.pdf

It should give you more info.

regards,

Roberto

Ahhh!!! That's what I needed!!! Perfect... I'm also getting the hang of the FPGA interface... Thanks Roberto!

Hi All

I am looking for the contact with this generous AVS member, who could sell me one of his blank PC Boards ... Would you please contact me by mail ?

I already ordered one EVK board for SDI mod but I do not know when I will receive it, so if this generous person could sell me one blank board, it will be very helpful to continue my adventure.:D :D

Thanks in advance.

To the generous member:D :D :D

I sent you an e-mail but returned. The adresse you gave me does not seem to be correct, so I sent you a PM.

Does this logic look any better?

Break down of NTSC scanline:
I can get the start of the EAV from the HSYNC...
set to FF 1 clock cycle
set to 00 2 clock cycle
set to XX 1 clock cycle
set counter to 268... count down
set to FF 1 clock cycle
set to 00 2 clock cycle
set to XX 1 clock cycle
wait for HSYNC to go HI, repeat.

I think I will need the VSYNC to format the XX? Right?

Do I need to use buffers for this? Or can I insert on the fly? I'd like not to have to use any buffers in this... just counters and gates...

To me the logic looks good.
In regards to the XX, please read the pdf in the above link.

regards,

Roberto

You the man, Roberto! I'll read it in a bit... thanks again!

Ok :)

after reading it self a bit more.

the XX is build up as follow;

1 F V H P3 P2 P1 P0

F = field, I think you need a counter again which is started by the V sync and counts the number of scanlines.
V = Vsync
H = Hsync
P3 / P0 = Protection bits. Glimmie said they don't matter.

To go dieper into the F;

After the Vsync triggers (H to L or L to H) wait 4 scanlines before setting the F bit to L (ODD). wait until the Vsync triggers again, wait 3 scanlines before setting the F bit to H (EVEN). wait until the Vsync triggers again and repeat above.

The problem is that there could be a mismatch between the source fields and the fields you generate. I don't know the impact.

regards,

Roberto

No, I don't "think" they are used. I'm not really sure. There may be some product out there that does utilize them and may get all upset if they are missing, i.e. set to 00 or FF. EDH came along a few years later and greatly surpasses the capability of this primitive error reporting scheme.

As we are using this stuff in a limited system, if it works without them, then great. I would never design a product for sale however without including them.