Guide to Building a HTPC, Workstation and Server - Page 4

______________
Table of Contents
¯¯¯¯¯¯¯¯¯¯¯¯¯¯

• Preface

1. History
2. P6 Microarchitecture
3. NetBurst Microarchitecture
4. Mobile Microarchitecture
5. Core Microarchitecture
   • Desktop
   • Server
   • Mobile
6. Atom Microarchitecture
7. Nehalem Microarchitecture

______
Preface
¯¯¯¯¯¯

The purpose of this part is list recent Intel chips according to microarchitectures since P6 for reference. (A microarchitecture is the design and layout of a microprocessor.) In-depth expositions of each microarchitecture and each CPU family are found in articles in References.

___________________
2. P6 Microarchitecture
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

The P6 microarchitecture is the sixth generation x86 architecture of Intel released in 1995, which lasted until 2000, then revived in the mobile microarchitecture in 2003 with the release of the Pentium M line of processors, which was in turn succeeded by the Core microarchitecture in 2006. (x86 or 80x86 is the generic name of microprocessor architecture developed by Intel since the Intel 8086 processor in 1978.) This was a completely new architecture featuring implementation of the RISC technology, on-die L2 cache, etc. The chip families based on this architecture are:

• Pentium Pro, used mostly in workstations and servers
  
  
  • P6, released on November 1, 1995, 500 nm and 350 nm processes, Socket 8
  
  
• Pentium II, actually low-end Pentium Pro, but re-branded
  
  
  • Klamath, released on May 7, 1997, 350 nm process, Slot 1
  • Deschutes, released on February 26, 1998, 250 nm process, Slot 1
  
  
• Pentium III
  
  
  • Katmai, released on February 26, 1999, 250 nm process, Slot 1
  • Coppermine, released on October 25, 1999, 180 nm process, Slot 1/Socket 370
  • Tualatin, released on June 19, 2001, 130 nm process, Socket 370

Celeron (a value desktop CPU line), Xeon (a server CPU line) and Mobile Pentium II/III (mobile CPU lines) were also introduced based on Pentium II/III cores.

By the way, the brand name Pentium first appeared in the fifth generation x86 architecture (codenamed P5) in March 1993.

________________________
3. NetBurst Microarchitecture
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

The Intel NetBurst microarchitecture is the successor to the P6 microarchitecture introduced in 2000. The architecture features deep pipeline, higher clock speeds, larger die size, etc. Intel expected 10GHz with this architecture, but eventually abandoned it because of increasing power dissipation with higher clock speeds. The chip families based on NetBurst are

• Pentium 4
  
  
  • Willamette, released on November 20, 2000, 180 nm process, Socket 423/478
  • Northwood, released on January 7, 2002, 130 nm process, Socket 478
  • Prescott (the last processor identified by a clock speed), released on February 2, 2004, 90 nm process, Socket 478
  • Prescott (500 Series), released on June 21, 2004 (with the 915 Express chipset), 90 nm process, Socket 775
  • Prescott 2M (600 Series), released on February 20, 2005, 90 nm process, EM64T, Socket 775
  • Cedar Mill (6x1 Series), released on January 18, 2006, 65 nm process, Socket 775
• Pentium D is the first announced dual-core desktop processor.
  
  
  • Smithfield (800 Series), released on May 26, 2005, two Prescott cores on a single die, 90 nm process, Socket 775
  • Presler (900 Series), released on January 6, 2006, two Cedar Mill dies on a single package, 65 nm process, Socket 775

There are also Extreme Editions, Celeron, Celeron D (single-core!), Xeon, Mobile Pentium 4 and Mobile Pentium 4 - M based on Pentium 4 and/or Pentium D cores. Intel is releasing NetBurst-based Dual-Core Xeon 7100 Series (Tulsa) that may be the last NetBurst-based CPU line.

_________
References
¯¯¯¯¯¯¯¯¯
NetBurst Microarchitecture

• AnandTech – Intel's NetBurst Architecture
• Ars Technica – The Pentium: An Architectural History of the World's Most Famous Desktop Processor (Part I) (July 11, 2004)
• Ars Technica – The Pentium: An Architectural History of the World's Most Famous Desktop Processor (Part II) (July 26, 2004)
• X-bit labs – NetBurst 1
• X-bit labs – NetBurst 2
• X-bit labs – NetBurst 3

Intel Dual-Core Processors

• AnandTech – Intel's Dual Core Strategy, Oct. 2004
• Ars Technica – Multicore, dual-core, and the future of Intel (September 13, 2004)

______________________
4. Mobile Microarchitecture
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

Intel's mobile microarchitecture was first implemented in the Pentium M mobile processor released in March 2003. Pentium M is not a low-power version of Pentium 4 but a modified version of Pentium III Tualatin optimized for power efficiency. It runs at a lower clock speed than Pentium 4 but with a similar performance. Then came Intel Core in January 2006 that brought dual core into notebooks with 65 nm technology. That was also a preliminary step to the next desktop Intel Core microarchitecture.

• Pentium M
  
  
  • Banias (vanilla and 705), released on March 12, 2003 as part of the Centrino mobile technology, 130 nm process, FSB 400MTps, Socket 479
  • Dothan (700 Series), released on May 10, 2004, 90 nm process, FSB 533MTps, Socket 479
  
  
• Core Duo (Yonah), released on January 5, 2006. Dual-core, 65 nm, [VT, EIST, XD Bit], Socket M (479 pins, but different layout from Socket 479)
  
  
  • Standard Voltage, FSB 533/667MTps, 31W
    • T2050: 1.60GHz = 133MHz x 12, 2MB L2, [no VT]
    • T2250: 1.73GHz = 133MHz x 13, 2MB L2, [no VT]
    • T2300E: 1.66GHz = 166MHz x 10, 2MB L2, [no VT]
    • T2300: 1.66GHz = 166MHz x 10, 2MB L2
    • T2400: 1.83GHz = 166MHz x 11, 2MB L2
    • T2500: 2.00GHz = 166MHz x 12, 2MB L2
    • T2600: 2.16GHz = 166MHz x 13, 2MB L2
    • T2700: 2.33GHz = 166MHz x 14, 2MB L2
  • Low Voltage, FSB 667MTps, 15W
    • L2300: 1.50GHz = 166MHz x 9, 2MB L2
    • L2400: 1.66GHz = 166MHz x 10, 2MB L2
    • L2500: 1.83GHz = 166MHz x 11, 2MB L2
  • Ultra Low Voltage, FSB 533MTps, 9W
    • U2400: 1.06GHz = 133MHz x 8, 2MB L2
    • U2500: 1.20GHz = 133MHz x 9, 2MB L2
  
  
• Core Solo (Yonah), released on January 5, 2006. Single-core (the same die as Core Duo with only one core active), 65 nm, Socket M
  
  
  • Standard Voltage, FSB 667MTps, 27W, [EIST, XD Bit]
    • T1300: 1.66GHz = 166MHz x 10, 2MB L2
    • T1350: 1.86GHz = 133MHz x 14, 2MB L2
    • T1400: 1.83GHz = 166MHz x 11, 2MB L2
  • Ultra Low Voltage, FSB 533MTps, 5.5W, [VT, EIST, XD Bit]
    • U1300: 1.06GHz = 133MHz x 8, 2MB L2
    • U1400: 1.20GHz = 133MHz x 9, 2MB L2
  
  
• Celeron M (400 Series, Yonah-based), released in April and May 2006. Single-core, 65 nm, [XD Bit], Socket M
  
  
  • Standard Voltage, FSB 533MTps, 27W
    • 410: 1.46GHz = 133MHz x 11, 1MB L2
    • 420: 1.60GHz = 133MHz x 12, 1MB L2
    • 430: 1.73GHz = 133MHz x 13, 1MB L2
    • 440: 1.86GHz = 133MHz x 14, 1MB L2
    • 450: 2.00GHz = 133MHz x 15, 1MB L2
  • Ultra Low Voltage, FSB 533MTps, 5.5W
    • 423: 1.06GHz = 133MHz x 8, 1MB L2

There are also Celeron M 300 Series based on Banias and Dothan and Dual-Core Xeon LV/ULV based on Yonah.

_________
References
¯¯¯¯¯¯¯¯¯
Intel's Mobile Microarchitecture

• AnandTech – Pentium M
• AnandTech – Yonah Preview 1
• AnandTech – Yonah Preview 2
• AnandTech – Core Duo

_____________________
5. Core Microarchitecture
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

The Intel Core microarchitecture is the current Intel microarchitecture, previously known as Next Generation Microarchitecture (NGMA). This is the direct successor to Intel's mobile microarchitecture and has little in common with the NetBurst microarchitecture. It features relatively low frequencies but improved other functions such as smarter prefetch and cache, resulting in increased performance and increasing energy efficiency.

Some of Intel's T's (Technologies) or *T's (star T's, Advanced Technologies) and other technologies embedded in today's microprocessors are:

• Hyper-Threading Technology (HT) enables one physical processor to appear and behave as two virtual processors to the operating system. Currently none of Core 2 cores supports this technology.
• Virtualization Technology (VT) enables one hardware platform to function as multiple "virtual" platforms.
• Enhanced Intel SpeedStep Technology (EIST) allows the system to dynamically adjust processor voltage and core frequency, which can result in decreased average power consumption and decreased average heat production. An equivalent of AMD's Cool'n'Quiet Technology.
• Extended Memory 64 Technology (EM64T) is Intel's name of the 64-bit microprocessor architecture developed by AMD.
• Execute Disable Bit (XD Bit) segregates instructions and data in memory to prevent certain classes of malicious software from taking over computers. The same as No Execute Bit (NX Bit) or Enhanced Virus Protection (EVP) in AMD's term.
• Trusted Execution Technology (TXT) will be introduced in 2007 and is designed to protect sensitive information from software attacks.

_________________
Desktop Processors
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

LGA775 – 65 nm

• Core 2 Duo (Conroe), first released on July 27, 2006. Dual-core, 65 nm, FSB 1066/1333MTps, 4MB L2 cache, [VT, EIST, EM64T, XD Bit]
  
  
  • E6300: 1.86GHz = 266MHz x 7, 2MB L2, 65W
  • E6320: 1.86GHz = 266MHz x 7, 65W (April 22, 2007)
  • E6400: 2.13GHz = 266MHz x 8, 2MB L2, 65W
  • E6420: 2.13GHz = 266MHz x 8, 65W (April 22, 2007)
  • E6600: 2.40GHz = 266MHz x 9, 65W
  • E6700: 2.66GHz = 266MHz x 10, 65W
  • E6540: 2.33GHz = 333MHz x 7, 65W, (July 22, 2007)
  • E6550: 2.33GHz = 333MHz x 7, 65W, [TXT] (July 22, 2007)
  • E6750: 2.66GHz = 333MHz x 8, 65W, [TXT] (July 22, 2007)
  • E6850: 3.00GHz = 333MHz x 9, 65W, [TXT] (July 22, 2007)
  
  
• Core 2 Extreme (Conroe), released on July 27, 2006. Dual-core, 65 nm, FSB 1066MTps, 4MB L2 cache, unlocked multiplier, [VT, EIST, EM64T, XD Bit]
  
  
  • X6800: 2.93GHz = 266MHz x 11, 75W
  
  
• Core 2 Quad (Kentsfield). Quad-core (two Conroe dies on a single package), 65 nm, FSB 1066MTps, 2 x 4MB L2 cache, [VT, EIST, EM64T, XD Bit]
  
  
  • Q6600: 2.40GHz = 266MHz x 9, 105W (SL9UM, B3; January 8, 2007) / 95W (SLACR, G0; July 22, 2007 )
  • Q6700: 2.66GHz = 266MHz x 10, 95W (July 22, 2007)
  
  
• Core 2 Extreme (Kentsfield). Quad-core (two Conroe dies on a single package), 65 nm, FSB 1066/1333MTps, 2 x 4MB L2 cache, unlocked multiplier, [VT, EIST, EM64T, XD Bit]
  
  
  • QX6700: 2.66GHz = 266MHz x 10, 130W (November 2, 2006)
  • QX6800: 2.93GHz = 266MHz x 11, 130W (April 9, 2007)
  • QX6850: 3.00GHz = 333MHz x 9, 130W (July 16, 2007)
  
  
• Core 2 Duo (Allendale), first released on January 21, 2007. Dual-core, 65 nm, FSB 800MTps, 2MB L2 cache, [EIST, EM64T, XD Bit]
  
  
  • E4300: 1.80GHz = 200MHz x 9, 65W
  • E4400: 2.00GHz = 200MHz x 10, 65W (April 22, 2007)
  • E4500: 2.20GHz = 200MHz x 11, 65W (July 22, 2007)
  • E4600: 2.40GHz = 200MHz x 12, 65W (October 21, 2007)
  • E4700: 2.60GHz = 200MHz x 13, 65W (March 2, 2008)
  
  
• Pentium Dual-Core (E2000 Series, Conroe-1M), first released in June 3, 2007. Dual-core, 65 nm, FSB 800MTps, 1MB L2 cache, [EIST, EM64T, XD Bit]
  
  
  • E2140: 1.60GHz = 200MHz x 8, 65W
  • E2160: 1.80GHz = 200MHz x 9, 65W
  • E2180: 2.00GHz = 200MHz x 10, 65W (August 26, 2007)
  • E2200: 2.20GHz = 200MHz x 11, 65W (December 2, 2007)
  • E2220: 2.40GHz = 200MHz x 11, 65W (March 2, 2008)
  
  
• Celeron Dual-Core (E1000 Series, Conroe-1M), first released on January 20, 2008. Dual-core, 65 nm, FSB 800MTps, 512KB L2 cache, [EM64T, XD Bit]
  
  
  • E1200: 1.60GHz = 200MHz x 8, 65W
  • E1400: 2.00GHz = 200MHz x 10, 65W (May 11, 2008)
  
  
• Celeron (400 Series, Conroe-L), first released on June 3, 2007. Single-core, 65 nm, FSB 800MTps, 512KB L2 cache, [EM64T, XD Bit]
  
  
  • 420: 1.60GHz = 200MHz x 8, 35W
  • 430: 1.80GHz = 200MHz x 9, 35W
  • 440: 2.00GHz = 200MHz x 10, 35W

LGA775 – 45 nm

• Core 2 Duo (Wolfdale), released on January 20, 2008. Dual-core, 45 nm, FSB 1333MTps, 6MB L2 cache, [VT, EIST, EM64T, XD Bit, TXT]
  
  
  • E8190: 2.66GHz = 333MHz x 8, 65W, [no VT, no TXT]
  • E8200: 2.66GHz = 333MHz x 8, 65W
  • E8300: 2.83GHz = 333MHz x 8.5, 65W (April 20, 2008)
  • E8400: 3.00GHz = 333MHz x 9, 65W
  • E8500: 3.16GHz = 333MHz x 9.5, 65W
  
  
• Core 2 Quad (Yorkfield), released in Q1 2008. Quad-core (two Wolfdale dies on a single package), 45 nm, FSB 1333MTps, 2 x 6MB L2 cache, [VT, EIST, EM64T, XD Bit]
  
  
  • Q9300: 2.50GHz = 333MHz x 7.5, 95W, 2 x 3MB L2
  • Q9450: 2.66GHz = 333MHz x 8, 95W
  • Q9550: 2.83GHz = 333MHz x 8.5, 95W
  
  
• Core 2 Extreme (Yorkfield), first released on November 12, 2007. Quad-core (two Wolfdale dies on a single package), 45 nm, FSB 1333MTps, 2 x 6MB L2 cache, unlocked multiplier, [VT, EIST, EM64T, XD Bit]
  
  
  • QX9650: 3.00GHz = 333MHz x 9, 130W
  • QX9770: 3.20GHz = 400MHz x 8, 136W (January 20, 2008)
  
  
• Core 2 Duo (Wolfdale-3M), to be released in Q2 2008. Dual-core, 45 nm, FSB 1066MTps, 3MB L2 cache, [EIST, EM64T, XD Bit]
  
  
  • E7200: 2.53GHz = 266MHz x 9.5, 65W
  
  
• Pentium Dual-Core (Wolfdale-2M), to be released in August 2008. Dual-core, 45 nm, FSB 800MTps, 2MB L2 cache, [EIST, EM64T, XD Bit]
  
  
  • E5200: 2.50GHz = 200MHz x 12.5, 65W

Skulltrail Platform

The Intel Skulltrail platform is a dual-socket, multi-core PC platform consisting of two LGA771 sockets, a pair of Yorkfield processors and Intel 5400 (Seaburg) DP server chipset (hence pricey FB-DIMM is required). It features 2 nForce 100 PCI Express bridges, supporting 4 PCI Express x16 links. Thus it is called 8x4 (8 CPU cores and 4 GPU cores). It's Intel's version of the AMD QuadFX platform.

• Core 2 Extreme (Yorkfield), released in Q1 2008. Quad-core (two Wolfdale dies on a single package), 45 nm, FSB 1600MTps, 2 x 6MB L2 cache, unlocked multiplier, [VT, EIST, EM64T, XD Bit]
  
  
  • QX9775: 3.20GHz = 400MHz x 8, 150W

________________
Server Processors
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

UP – 65 nm

Processors for UP (uni-processor) system are the same as desktop processors with LGA775 socket.

• Dual-Core Xeon 3000 Series (Conroe), first released in October 2006. Dual-core, 65 nm, FSB 1066MTps, 4MB L2 cache, [VT, EIST, EM64T, XD Bit]
  
  
  • 3040: 1.86GHz = 266MHz x 7, 2MB L2, 65W
  • 3050: 2.13GHz = 266MHz x 8, 2MB L2, 65W
  • 3060: 2.40GHz = 266MHz x 9, 65W
  • 3065: 2.33GHz = 333MHz x 7, 65W
  • 3070: 2.66GHz = 266MHz x 10, 65W
  • 3075: 2.66GHz = 333MHz x 8, 65W
  • 3085: 3.00GHz = 333MHz x 9, 65W
  
  
• Quad-Core Xeon 3200 Series (Kentsfield), released on January 7, 2007. Quad-core, 65 nm, FSB 1066MTps, 2 x 4MB L2 cache, [VT, EIST, EM64T, XD Bit]
  
  
  • X3210: 2.13GHz = 266MHz x 8, 105W
  • X3220: 2.40GHz = 266MHz x 9, 105W
  • X3230: 2.66GHz = 266MHz x 10, 95W

DP – 65 nm

DP (dual-processor) systems use LGA771 socket with Bensley platform.

• Dual-Core Xeon 5100 Series (Woodcrest), released on June 25, 2006. Dual-core, 65 nm, FSB 1066/1333MTps, 4MB L2 cache, [VT, EIST, EM64T, XD Bit]
  
  
  • 5110: 1.60GHz = 266MHz x 6, 65W
  • 5120: 1.87GHz = 266MHz x 7, 65W
  • 5130: 2.00GHz = 333MHz x 6, 65W
  • 5140: 2.33GHz = 333MHz x 7, 65W
  • 5150: 2.66GHz = 333MHz x 8, 65W
  • 5160: 3.00GHz = 333MHz x 9, 80W
  • LV 5128: 1.86GHz = 266MHz x 7, 40W
  • LV 5138: 2.13GHz = 266MHz x 8, 35W
  • LV 5148: 2.33GHz = 333MHz x 7, 40W
  
  
• Quad-Core Xeon 5300 Series (Clovertown), first released on November 14, 2006. Quad core (two Woodcrest dies on a single package), 65 nm, FSB 1066/1333MTps, 2 x 4MB L2 cache, [VT, EIST, EM64T, XD Bit]
  
  
  • L5310: 1.60GHz = 266MHz x 6, 50W (March 12, 2007)
  • E5310: 1.60GHz = 266MHz x 6, 80W
  • L5320: 1.86GHz = 266MHz x 7, 50W (March 12, 2007)
  • E5320: 1.86GHz = 266MHz x 7, 80W
  • L5335: 2.00GHz = 333MHz x 6, 50W (August 13, 2007)
  • E5335: 2.00GHz = 333MHz x 6, 80W
  • E5345: 2.33GHz = 333MHz x 7, 80W
  • X5355: 2.66GHz = 333MHz x 8, 120W
  • X5365: 3.00GHz = 333MHz x 9, 120W (August 13, 2007)

UP – 45 nm

Processors for UP (uni-processor) system are the same as desktop processors with LGA775 socket.

• Dual-Core Xeon 3100 Series (Wolfdale), released on January 20, 2008. Dual-core, 45 nm, FSB 1333MTps, 6MB L2 cache, [VT, EIST, EM64T, XD Bit]
  
  
  • E3110: 3.00GHz = 333MHz x 9, 65W
  
  
• Quad-Core Xeon 3300 Series (Yorkfield), released on Q1 2008. Quad core (two Wolfdale dies on a single package), 45 nm, FSB 1333MTps, 2 x 6MB L2 cache, [VT, EIST, EM64T, XD Bit]
  
  
  • X3320: 2.50GHz = 333MHz x 7.5, 2 x 3MB L2, 95W
  • X3350: 2.66GHz = 333MHz x 8, 95W
  • X3360: 2.83GHz = 333MHz x 8.5, 95W

DP – 45 nm

• Dual-Core Xeon 5200 Series (Wolfdale-DP), released on November 12, 2007. Dual-core, 45 nm, FSB 1066/1333/1600MTps, 6MB L2 cache, [VT, EIST, EM64T, XD Bit]
  
  
  • E5205: 1.86GHz = 266MHz x 7, 65W
  • X5260: 3.33GHz = 333MHz x 10, 80W
  • X5272: 3.40GHz = 400MHz x 8.5, 80W
  
  
• Quad-Core Xeon 5400 Series (Harpertown), released on November 12, 2007. Quad core (two Wolfdale-DP dies on a single package), 45 nm, FSB 1333/1600MTps, 2 x 6MB L2 cache, [VT, EIST, EM64T, XD Bit]
  
  
  • E5405: 2.00GHz = 333MHz x 6, 80W
  • E5405: 2.00GHz = 333MHz x 6, 80W
  • E5410: 2.33GHz = 333MHz x 7, 80W
  • E5420: 2.50GHz = 333MHz x 7.5, 80W
  • E5430: 2.66GHz = 333MHz x 8, 80W
  • E5440: 2.83GHz = 333MHz x 8.5, 80W
  • E5450: 3.00GHz = 333MHz x 9, 80W
  • X5450: 3.00GHz = 333MHz x 9, 120W
  • X5460: 3.16GHz = 333MHz x 9.5, 120W
  • E5462: 2.80GHz = 400MHz x 7, 80W
  • E5472: 3.00GHz = 400MHz x 7.5, 80W
  • X5472: 3.00GHz = 400MHz x 7.5, 120W
  • X5482: 3.20GHz = 400MHz x 8, 150W

MP (4-Way) – 65 nm

The current Intel MP (multi-processor) system use the Caneland platform with four Socket 604 and four independent FSB.

• Dual-Core Xeon 7200 Series (Tigerton-DC), released on ?. Dual-core, 65 nm, FSB 1066MTps, 8MB L2 cache, [VT, EIST, EM64T, XD Bit]
  
  
  • E7210: 2.40GHz = 266MHz x 9, 80W
  • E7220: 2.93GHz = 266MHz x 11, 80W
  
  
• Quad-Core Xeon 7300 Series (Tigerton), released on ?. Quad-core, 65 nm, FSB 1066MTps, [VT, EIST, EM64T, XD Bit]
  
  
  • E7310: 1.60GHz = 266MHz x 6, 4MB L2, 80W
  • E7320: 2.13GHz = 266MHz x 8, 4MB L2, 80W
  • E7330: 2.40GHz = 266MHz x 9, 6MB L2, 80W
  • E7340: 2.40GHz = 266MHz x 9, 8MB L2, 80W
  • L7345: 1.86GHz = 266MHz x 7, 8MB L2, 50W
  • X7350: 2.93GHz = 266MHz x 11, 8MB L2, 130W

MP (4-Way) – 45 nm

A 45 nm successor to Tigerton is Dunnington, expected in Q4 2008. This is a native 6-core chip (a monolithic chip consisting of 3 pairs of Core 2 processors) and pin-compatible with Tigerton.

________________________
7. Nehalem Microarchitecture
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

Nehalem Microarchitecture is an architecture that succeeds Core Microarchitecture and is planned to be released in Q4 2008. It is designed by the developing team at Oregon (who designed P6 and NetBurst microarchitectures too). Despite its location, Nehalem Microarchitecture is based on Core Microarchitecture (which was designed by the Israeli team) with several new technologies:

• A new processor bus, called Intel QuickPath interconnect, that features point-to-point serial bus topology, similar to PCI Express and HyperTransport (AMD adopted it in 2003!).
• IMC (Integrated Memory Controller), called Intel QuickPath memory controller, up to triple channel DDR3.
• Performance improvement by adding new functions such as
  • SMT (Simultaneous Multi-Threading), the revival of HT (HyperThreading) in Pentium 4
  • New 3-level cache hierarchy, L2, L2 (new 256KB/core), L3 (8MB fully-shared)
  • New 2-level TLB (Translation Lookaside Buffer) hierarchy
  • L2 branch predictor

_________
References
¯¯¯¯¯¯¯¯¯

• DailyTech – Intel Life after Conroe (June 20, 2006)
• PC Watch – Topics on the Intel 3 Series chipset and a new chipset in 2008 (June 7, 2007)
• X-bit labs – Intel Readies New Memory Controller for Nehalem Chips (June 10, 2007)
• PC Watch – IDFで公開された「Nehalem」の内部アーキテクチャ (April 3, 2008)

Reserved 102

Reserved 103

Reserved 104

Reserved 105

Reserved 106

Reserved 107

Reserved 108

Reserved 109

Reserved 110

Reserved 111

Reserved 112

Reserved 113

Reserved 114

Reserved 115

Reserved 116

Reserved 117

Reserved 118

Reserved 119

Reserved 120