Originally Posted by nvidio
Of course I already knew that. Because, last time I checked, I was the guy who pointed that out to you in the first place.
Now you're just making me laugh. So you already knew, and I already knew it, but you pointed it out to me after I pointed it out to you? My head is spinning.
No, I am not trying to nitpick. The analog section of the ESS chip requires cleanliness in the 3.3V power signal that feeds it. Says so in the documnet I linked. Again, I can only guess but... shouldn't this be easy for you to verify in a DBT by ultimately putting your money where your mouth is? Or have I just been missing your point again somehow?
I don't have the time or the setup (currently) to conduct a DBT on this. I don't even have the DAC in question. Besides, what good would it do? If I did a DBT and reported I couldn't tell them apart, you'd just say "well just because you can't doesn't mean I can't." Or you'd say my DBT procedure or setup was flawed.
Eureka. And, how exactly was it that you expected to achieve clock cleanliness without also feeding a clean power signal to the clock?
I know. I've read the application notes, remember?
Congrats on reading the app notes, I guess?
I just read them too, for the first time, and lo and behold, what's all that talk about using regulators for its power voltage supplies?
Looks like I was right on the money the whole time.
As for feeding a clean power signal to the clock, I'm not sure what you're referring to there. What power is there for the clock? Isn't it a crystal connected directly to the DAC chip? If you're talking about the other voltages feeding power to the chip, again, the key word is regulators.
Looks like the app note substantiates everything I've been saying. Not surprising considering how many app notes I've read over the years and how many DAC ICs I implemented on boards in various products.